Efficient test cost reduction procedure for parallel-serial scan circuits

Authors
Solana, JM
Citation
Jm. Solana, Efficient test cost reduction procedure for parallel-serial scan circuits, ELECTR LETT, 37(21), 2001, pp. 1277-1278
Citations number
4
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
ELECTRONICS LETTERS
ISSN journal
00135194 → ACNP
Volume
37
Issue
21
Year of publication
2001
Pages
1277 - 1278
Database
ISI
SICI code
0013-5194(20011011)37:21<1277:ETCRPF>2.0.ZU;2-B
Abstract
An efficient test generation procedure aimed. at reducing test application cost in parallel-serial scan (PASE-scan) circuits is presented. The procedu re is based on the structure and configuration of this type of Full-scan ci rcuits. The results obtained with a set of ISCAS89 benchmark circuits are p rovided, showing the effectiveness of this technique as regards test clock reduction.