An embedded 32-b microprocessor core for low-power and high-performance applications

Citation
Lt. Clark et al., An embedded 32-b microprocessor core for low-power and high-performance applications, IEEE J SOLI, 36(11), 2001, pp. 1599-1608
Citations number
11
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE JOURNAL OF SOLID-STATE CIRCUITS
ISSN journal
00189200 → ACNP
Volume
36
Issue
11
Year of publication
2001
Pages
1599 - 1608
Database
ISI
SICI code
0018-9200(200111)36:11<1599:AE3MCF>2.0.ZU;2-I
Abstract
An embedded RISC microprocessor core fabricated in a six-layer metal 0.18-m um CMOS process implementing the ARM (TM) V.5TE instruction set is describe d. The core described is the first implementation of the Intel XScale Micro architecture (TM). (ARM is a registered trademark of Advanced RISC Machines , Ltd.) The microprocessor core, which includes caches, memory management u nits, and a bus controller, comprises a hard-embedded block 16.77 mm(2) in size. The implementation is primarily custom logic in a variety of circuit styles. The processor dissipates 450 mW at 1.3 V, 600 MHz, and scales betwe en 55 mW at 0.7 V, 200 MHz, and 900 mW at 1.65 V, 800 MHz. Architectural pe rformance is 1000 MIPS at 800 MHz with efficiency ranging from over 850 MIP S/W at 1.65 V to over 4500 MIPS/W at 0.75 V. Architectural and circuit desi gn approaches for low power and high performance are described and measured results from the initial implementation are shown. The first implementatio n VLSI chip has a 3.3-V pin interface and supports a 0.75-1.65-V core volta ge range.