The first MAJC microprocessor: A dual CPU system-on-a-chip

Citation
A. Kowalczyk et al., The first MAJC microprocessor: A dual CPU system-on-a-chip, IEEE J SOLI, 36(11), 2001, pp. 1609-1616
Citations number
6
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE JOURNAL OF SOLID-STATE CIRCUITS
ISSN journal
00189200 → ACNP
Volume
36
Issue
11
Year of publication
2001
Pages
1609 - 1616
Database
ISI
SICI code
0018-9200(200111)36:11<1609:TFMMAD>2.0.ZU;2-B
Abstract
The first implementation of MAJC architecture achieves high performance by using very long instruction word (VLIW), single instruction multiple data ( SIMD), and chip multiprocessing. The chip integrates two processors, a memo ry controller, two high-speed parallel I/O interfaces, and a PCI controller . The chip, fabricated in a 0.22-mum CMOS process with six layers of copper interconnect, contains 13 million transistors and operates at 500 MHz. It is packaged in a 624-pin ceramic column grid array using flip-chip assembly technology.