The first implementation of MAJC architecture achieves high performance by
using very long instruction word (VLIW), single instruction multiple data (
SIMD), and chip multiprocessing. The chip integrates two processors, a memo
ry controller, two high-speed parallel I/O interfaces, and a PCI controller
. The chip, fabricated in a 0.22-mum CMOS process with six layers of copper
interconnect, contains 13 million transistors and operates at 500 MHz. It
is packaged in a 624-pin ceramic column grid array using flip-chip assembly
technology.