A 2.5-GHz four-phase clock generator with scalable no-feedback-loop architecture

Citation
K. Yamaguchi et al., A 2.5-GHz four-phase clock generator with scalable no-feedback-loop architecture, IEEE J SOLI, 36(11), 2001, pp. 1666-1672
Citations number
14
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE JOURNAL OF SOLID-STATE CIRCUITS
ISSN journal
00189200 → ACNP
Volume
36
Issue
11
Year of publication
2001
Pages
1666 - 1672
Database
ISI
SICI code
0018-9200(200111)36:11<1666:A2FCGW>2.0.ZU;2-S
Abstract
An accurate yet simple multiphase clock generator has been developed by usi ng a delay compensation technique based on phase interpolation that supplie s a multiphase clock signal without increasing local circuit area. This gen erator is applied to the 2.5-GHz four-phase clock distribution of a 5-Gb/s x 8-channel receiver fabricated with 0.13-mum CMOS technology. The four-pha se generator in the receiver consumes 30 mW and occupies only 0.009 mm(2). It requires only 1.5 clock cycles to produce accurate phase differences and can operate from 1.5 to 2.8 GHz, with a range of phase error within +/-5 d egrees.