A low-jitter 125-1250-MHz process-independent and ripple-poleless 0.18-mu m CMOS PLL based on a sample-reset loop filter

This paper describes a low-jitter phase-locked loop (PLL) implemented in a 0.18-mum CMOS process. A sample-reset loop filter architecture is used that averages the oscillator proportional control current which provides the fe edforward zero over an entire update period and hence leads to a ripple-fre e control signal. The ripple-free control current eliminates the need for a n additional filtering pole, leading to a nearly 90 degrees phase margin wh ich minimizes input jitter peaking and transient locking overshoot. The PLL damping factor Is made Insensitive to process variations by making it depe ndent only upon a bandgap voltage and ratios of circuit elements. This ensu res tracking between the natural frequency and the stabilizing zero. The PL L has a frequency range of 125-1250 MHz, frequency resolution better than 5 00 kHz, and rms jitter less than 0.9% of the oscillator period.