A 116.7-mm(2) NAND flash memory having two modes, 1-Gb multilevel program c
ell (MLC) and high-performance 512-Mb single-level program cell (SLC) modes
, is fabricated with a 0.15-mum CMOS technology. Utilizing simultaneous ope
ration of four independent banks, the device achieves 1.6 and 6.9 MB/s prog
ram throughputs for MLC and SLC modes, respectively. The two-step bitline s
etup scheme suppresses the peak current below 60 mA. The wordline ramping t
echnique avoids program disturbance. The SLC mode uses the 0.5-V incrementa
l step pulse and self-boosting program inhibit scheme to achieve high progr
am performance, and the MLC mode uses 0.15-V incremental step pulse and loc
al self-boosting program inhibit scheme to tightly control the cell thresho
ld voltage V-th distributions. With the small wordline and bitline pitches
of 0.3 -mum and 0.36-mum, respectively, the cell V-th, shift due to the flo
ating gate coupling is about 0.2 V. The read margins between adjacent two p
rogram states are optimized resulting in the nonuniform cell V-th distribut
ion for MLC mode.