A dual-mode NAND flash memory: 1-Gb multilevel and high-performance 512-Mbsingle-level modes

Citation
T. Cho et al., A dual-mode NAND flash memory: 1-Gb multilevel and high-performance 512-Mbsingle-level modes, IEEE J SOLI, 36(11), 2001, pp. 1700-1706
Citations number
4
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE JOURNAL OF SOLID-STATE CIRCUITS
ISSN journal
00189200 → ACNP
Volume
36
Issue
11
Year of publication
2001
Pages
1700 - 1706
Database
ISI
SICI code
0018-9200(200111)36:11<1700:ADNFM1>2.0.ZU;2-E
Abstract
A 116.7-mm(2) NAND flash memory having two modes, 1-Gb multilevel program c ell (MLC) and high-performance 512-Mb single-level program cell (SLC) modes , is fabricated with a 0.15-mum CMOS technology. Utilizing simultaneous ope ration of four independent banks, the device achieves 1.6 and 6.9 MB/s prog ram throughputs for MLC and SLC modes, respectively. The two-step bitline s etup scheme suppresses the peak current below 60 mA. The wordline ramping t echnique avoids program disturbance. The SLC mode uses the 0.5-V incrementa l step pulse and self-boosting program inhibit scheme to achieve high progr am performance, and the MLC mode uses 0.15-V incremental step pulse and loc al self-boosting program inhibit scheme to tightly control the cell thresho ld voltage V-th distributions. With the small wordline and bitline pitches of 0.3 -mum and 0.36-mum, respectively, the cell V-th, shift due to the flo ating gate coupling is about 0.2 V. The read margins between adjacent two p rogram states are optimized resulting in the nonuniform cell V-th distribut ion for MLC mode.