A 76-mm(2) 8-Mb chain ferroelectric memory

This paper demonstrates the first 8-Mb chain ferroelectric RAM (chain FeRAM ) with 0.25-mum 2-metal CMOS technology. A small die of 76 mm(2) and a high average cell/chip area efficiency of 57.4% have been realized by introduci ng not only chain architecture but also four new techniques: 1) a one-pitch shift cell realizes small cell size of 5.2 mum(2); 2) a new hierarchical w ordline architecture reduces row-decoder and plate-driver areas without an extra metal layer; 3) a small-area dummy cell scheme reduces dummy capacito r size to 1/3 of the conventional one; and 4) a new array activation scheme reduces dataline and second amplifier areas. As a result, the chain archit ecture with these new techniques reduces die size to 65% of that of the con ventional FeRAM. Moreover, a ferroelectric capacitor overdrive scheme enabl es sufficient polarization switching, without overbias memory cell array. T his scheme lowers the minimum operation voltage by 0.23 V, and enables 2.5- V V-dd operation. Thanks to fast cell plateline drive of chain architecture , the 8-Mb chain FeRAM has achieved the fastest random access time, 40 ns, and read/write cycle time, 70 us, at 3.0 V so far reported.