Universal-V-dd 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell

Authors
Osada, K Shin, JL Khan, M Liou, Y Wang, K Shoji, K Kuroda, K Ikeda, S Ishibashi, K
Citation
K. Osada et al., Universal-V-dd 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell, IEEE J SOLI, 36(11), 2001, pp. 1738-1744
Citations number
7
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE JOURNAL OF SOLID-STATE CIRCUITS
ISSN journal
00189200 → ACNP
Volume
36
Issue
11
Year of publication
2001
Pages
1738 - 1744
Database
ISI
SICI code
0018-9200(200111)36:11<1738:U03CUA>2.0.ZU;2-A
Abstract
A universal-V-dd 32-kB four-way-set-associative embedded cache has been dev eloped. A test cache chip was fabricated by using 0.18-mum enhanced CMOS te chnology, and it was found to continuously operate from 0.65 to 2.0 V Its o perating frequency and power are from 120 MHz and 1.7 mW at 0.65 V to 1.04 GHz and 530 mW at 2.0 V The cache is based on two new circuit techniques: a voltage-adapted timing-generation scheme with plural dummy cells for the w ider voltage-range operation, and use of a lithographically symmetrical cel l for lower voltage operation.