An 80/20-MHz 160-mW multimedia processor integrated with embedded DRAM, MPEG-4 accelerator, and 3-D rendering engine for mobile applications

A low-power multimedia processor for mobile applications is presented. An 8 0-MHz 32-b RISC with enhanced multiplier, two 20-MHz hardware accelerators with 7.125-Mb embedded DRAM for MPEG-4 visual SP@L1 decoding and 3-D graphi cs processing, 2-kB dual-port SRAM, and peripheral blocks are integrated to gether on a single chip. MPEG-4 SP@L1 video decoding and 3-D graphics rende ring with a 16-b depth-buffer alpha-blending double-buffering and gouraud-s hading features at 2.2-Mpolygons/s speed are realized with the help of the dedicated hardware accelerators. The architecture of the processor is optim ized in terms of power consumption and performance, and various low-power c ircuit techniques are adopted in each hardware block. The chip is implement ed using 0.18-mum embedded memory logic (EML) technology. Its area is 84 mm (2), and power consumption is 160 mW when all of the functions are activate d.