A 150-MHz graphics rendering processor with 256-Mb embedded DRAM

A 150-MHz graphics rendering processor with an integrated 256-Mb embedded D RAM, delivering a rendering rate of 75 M polygons/s, is presented. 287.5 M transistors are integrated on a 21.3 x 21.7 mm(2) die in a 0.18-mum embedde d DRAM CMOS process with six layers of metal. Design methodologies for hier archical electrical and physical design of this very large-scale IC, includ ing power distribution, fully hierarchical timing design, and verification utilizing a newly developed nonlinear model, clock design, propagation dela y, and crosstalk noise management in multimillimeter RC transmission lines, are presented.