VLSI implementation of a 100-mu W multirate FSK receiver

A very low-power frequency-shift keying (FSK) receiver has been designed fo r dual-purpose operation: deep space applications and general purpose baseb and processing. The receiver is based on a novel, almost all-digital archit ecture. It supports a wide range of data rates and is very robust against l arge and fast frequency offsets due to Doppler. The architecture utilizes s ubsampling and 1-b data processing together with an FFT-based detection sch eme to enable power consumption dramatically, lower than a conventional imp lementation. A system/hardware co-design approach allows the use of a numbe r of circuit-level power reduction techniques while still meeting system-le vel constraints. In particular, we designed a combination of fully parallel and word-serial decimation stages to simultaneously optimize power consump tion and silicon area. We also designed a very efficient FFT block that use s approximate arithmetic and pruning to greatly reduce overall complexity. Additional modules, such as direct digital frequency synthesizer (DDFS) and magnitude computation, have also been optimized in view of the targeted sy stem parameters: signal-to-noise ratio and bit-error rate. The entire archi tecture has been made maximally flexible and power efficient by utilizing l ocal clock gating and simple interstage handshaking mechanism. The receiver has been implemented in 0.25-mum CMOS technology and takes up under 1 mm(2 ). The power consumption is below 100 muW for data rates below 20 kb/s. Rat es up to 2 Mb/s are supported.