EXTRINSIC VERSUS INTRINSIC MODELS FOR FETS

The importance of a proper inclusion of parasitic source and drain res istances in various FET device models used in circuit simulation with SPICE is pointed out. Although a significant reduction in simulation t ime can be achieved using so-called extrinsic FET models, some problem s are encountered in cases where gate leakage current is present and i n simulating transients. Moreover, an intrinsic model with parasitics is more compatible with high frequency small signal equivalent circuit s.