CMOS compatible fabrication methods for submicron Josephson junction qubits

Citation
A. Potts et al., CMOS compatible fabrication methods for submicron Josephson junction qubits, IEE P-SCI M, 148(5), 2001, pp. 225-228
Citations number
14
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEE PROCEEDINGS-SCIENCE MEASUREMENT AND TECHNOLOGY
ISSN journal
13502344 → ACNP
Volume
148
Issue
5
Year of publication
2001
Pages
225 - 228
Database
ISI
SICI code
1350-2344(200109)148:5<225:CCFMFS>2.0.ZU;2-W
Abstract
The authors have developed two distinct processes for the fabrication of me soscopic Josephson junction qubits that are compatible with conventional CM OS processing. These devices, based on superconducting Al/Al2O3/Al tunnel j unctions, are fabricated by electron beam lithography using single-layer an d multi-layer resists. The new single-layer resist process is found to have significant advantages over conventional fabrication methods using suspend ed tri-layer shadow masks. It is simpler and more accurate to implement, an d avoids the significant areas of redundant metallisation that are an unavo idable by-product of the tri-layer shadow mask method.