Delay-insensitive gate-level pipelining

Gate-level pipelining (GLP) techniques are developed to design throughput-o ptimal delay-insensitive digital systems using NULL convention logic (NCL). Pipelined NCL systems consists of combinational, registration, and complet ion circuits implemented using threshold gates equipped with hysteresis beh avior. NCL combinational circuits provide the desired processing behavior b etween asynchronous registers that regulate wavefront propagation. NCL comp letion logic detects completed DATA or NULL output sets from each register stage. GLP techniques cascade registration and completion elements to syste matically partition a combinational circuit and allow controlled overlappin g of input wavefronts. Both full-word and bit-wise completion strategies ar e applied progressively to select the optimal size grouping of operand and output data bits. To illustrate the methodology, GLP is applied to a case s tudy of a 4-bit x 4-bit unsigned multiplier, yielding a speedup of 2.25 ove r the non-pipelined version, while maintaining delay insensitivity. (C) 200 1 Elsevier Science B.V. All rights reserved.