Adiabatic carry look-ahead adder with efficient power clock generator

Performance and characteristics of an adiabatic logic family are studied an d compared with those of combinational and pipelined static CMOS counterpar ts. An 8-bit adiabatic carry look-ahead adder and its combinational and pip elined static CMOS counterparts are designed using a 0.6-mum CMOS technolog y. The performance of each circuit is studied in terms of the maximum frequ ency of operation, the minimum voltage of operation, the circuit energy, co nsumption, and the switching noise generated by the circuit. Based on the s imulation results, depending on the operating frequency, the adiabatic adde r exhibits energy savings up to 87% compared with its combinational and pip elined static CMOS counterparts. It also exhibits a considerable reduction in switching noise, compared with its static CMOS counterparts, Practical i ssues in the design of power clock generators needed by adiabatic logic cir cuits are also explained. Synchronous and asynchronous power clock generato rs are designed and the more energy efficient circuit for the power clock g eneration is determined. The power clock generator exhibits a conversion ef ficiency of 77% at 10MHz operating frequency.