Novel PLL-based frequency synthesiser without using the frequency divider

A technique of implementing a PLL-based frequency synthesiser (FS) without using the frequency divider sub-circuit has been discussed. To generate the loop oscillator control signal, proportional to the phase mismatch between the reference signal and the synthesised signal (where the frequency of th e latter is a multiple of that of the former), the proposed structure uses a phase detector used in data clock recovery circuits with some modificatio n. The operating conditions of the proposed system have been analytically e xamined and the results of a prototype hardware experiment carried out arou nd 500kHz are given. The study confirms the possibility of designing a divi derless indirect FS with low power consumption and high spectral purity.