The authors propose a pulse width modulator (PWM) for a hearing instrument
(hearing aid) class D amplifier with emphases on low external component cou
nt, low cost. and low voltage and micropower operation. The PWM is based on
a novel master-slave architecture that features a self-error-correction me
chanism. This mechanism tunes the zero-input PWM output to 50% duty cycle,
thereby reducing the output DC bias current of the amplifier; expensive pos
t-fabrication calibration or trimming is unnecessary. The PWM is readily re
alised in a low-cost digital CMOS process and the input AC coupling capacit
or is realised on-chip, reducing the external component count. The high mat
ching requirement of the master and slave circuits is reduced by employing
a novel switching methodology that periodically interchanges the critical (
to matching) subcircuits of the master and slave circuits, without disrupti
ng the continuous operation of the PWM. Computer simulations and measuremen
ts on prototype ICs show that the zero-input PWM output duty cycle error is
less than or equal to2%, well within specifications, i.e. the DC output bi
as current (for R-L = 600 Ohm) is I-o = 83 muA at V-DD = 2.5 V (or equivale
nt to I-o = 22 muA at V-DD = 1.3 V). The PWM circuit draws 25 muA at V-DD =
2.5 V (or equivalent to 10 muA at V-DD = 1.3V.