Minimising power dissipation in partial scan sequential circuits

Recently a new test application strategy for minimising of power dissipatio n during test applications in full scan sequential circuits was proposed. T his paper investigates its applicability to partial scan sequential circuit s. It is shown that, when compared to full scan sequential circuits, partia l scan not only reduces the test area overhead and test application time, b ut also reduces the power dissipation during test applications and the comp utational time required for low power testable design space exploration.