Network on a chip: Modeling wireless networks with asynchronous VLSI

We introduce the notion of a network on a chip: a programmable asynchronous VLSI architecture for fast and efficient simulation of wireless networks. The approach is inspired by the remarkable similarity between networks and asynchronous VLSI. Our approach results in simulators that can evaluate net work scenarios much faster than real time, enabling a new class of network protocols that can dynamically change their behavior based on feedback from in situ simulation. We describe our simulation architecture, and present r esults that validate our approach.