Sf. Hsiao et Wr. Shiue, A new hardware-efficient algorithm and architecture for computation of 2-DDCTs on a linear array, IEEE CIR SV, 11(11), 2001, pp. 1149-1159
Citations number
18
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY
A new recursive algorithm with hardware complexity of O (log(2)N) is derive
d for fast computation of N x N 2-D discrete cosine transforms (2-D DCTs).
It first converts the original 2-D data matrices into 1-D vectors and then
employs different partition methods for the input and output indices in the
1-D vector space. Afterward, the algorithm computes the corresponding;2-D
complex DCT (2-D CCT) and then uses a post-addition step to produce simulta
neously two 2-D DCT outputs. The decomposed form of the 2-D recursive algor
ithm looks like a radix-4 fast Fourier transform algorithm. The common entr
ies in each row of the butterfly-like matrix are factored out in order to r
educe the number of multipliers needed during implementation. A new linear
architecture for the derived algorithm is presented which leads to a hardwa
re-efficient architectural design requiring only log, N complex multipliers
plus 3log(2)N complex adders/subtractors for the computation of a 2-D N x
N CCT.