High-throughput high-density mapping and spectrum analysis of transistor gate length variations in SRAM circuits

High-through put high-density mapping of gate length variations using stati c random-access memory (SRAM) as electronic test structures is reported. In the experiments direct measurements of bit-line currents revealed the indi vidual transistor gate length variations within every memory cell. With SRA M and its fast addressing circuits we can measure CD variations with measur ement time as fast as 5 mus per data point and spatial periodicities down t o 6 mum. Layout-dependent periodic errors were found to take up 30% to 90% of the total observed error variance, depending on the spatial frequency ra nge and specific measurement grid used. Peaks in the error spectrum were fo und to be related to the periodicities existing in the circuit layout. Lith ography simulations were done as efforts to identify the periodic error sou rces. It was found that proximity effects and pattern-dependent coma effect s contributed to a large percentage of the high spatial frequency errors ob served. By independent optical measurements of the poly mask, it was found that the CD error contributions from the mask are very small, and are negli gible when compared to the stepper-lens-induced CD errors.