An RTL design-space exploration method for high-level applications

Citation
Pc. Kao et al., An RTL design-space exploration method for high-level applications, IEICE T FUN, E84A(11), 2001, pp. 2648-2654
Citations number
21
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
ISSN journal
09168508 → ACNP
Volume
E84A
Issue
11
Year of publication
2001
Pages
2648 - 2654
Database
ISI
SICI code
0916-8508(200111)E84A:11<2648:ARDEMF>2.0.ZU;2-K
Abstract
In this paper. we present an RTL design-space exploration method for high-l evel applications. We formulate the RTL design-space exploration into a per formanced riven module selection problem. We devise a dynamic-programming a lgorithm to solve the problem. We present an exploration flow by integratin g commercial synthesis and layout tools with our proposed method. Experimen tal results have demonstrated that generating AT-curve for all modules is t he most time consuming task in the design-space exploration process. Using the proposed 3-point AT projection approach, our method can achieve on an a verage of 80% speed-up in run time and 90% accuracy in design estimation.