Timing driven gate duplication in technology independent phase

We propose a timing driven gate duplication algorithm for the technology in dependent phase. Our algorithm is a generalization of the gate duplication strategy suggested in [3]. Our technique gets a more global view by duplica ting multiple gates at a time. We compare the minimum circuit delay obtaine d by SIS [4] with the delay obtained by using our gate duplication. Results show that up to 11% improvement in delay can be obtained. Our algorithm do es not have an adverse effect on the overall synthesis time, indicating tha t gate duplication is an efficient strategy for timing optimization.