VLSI floorplanning with boundary constraints using corner block list representation

Boundary Constraints of VLSI floorplanning require a set of blocks to be pl aced along the boundaries of the chip. Thus, this set of blocks can be adja cent to 1/0 pads for external communication. Furthermore, these blocks are kept away from the central area so that they do not form blockage for inter nal routing. In the paper, we devise an algorithm of VLSI floorplanning wit h boundary constraints using a Corner Block List (CBL) representation [8]. We identify the necessary and sufficient conditions of the CBL representati on for the boundary constraints. We design a linear time approach to scan t he conditions and formulate a penalty function to punish the constraint vio lation. A simulated annealing process is adopted to optimize the floorplan. Experiments on MCNC benchmarks show promising results.