Optimization of test accesses with a combined BIST and external test scheme

External pins for tests are precious hardware resources because this number is strongly restricted. Cores are tested via test access mechanisms (TANIs ) such as a test bus architecture. When cores are tested via test buses whi ch have constant bit widths, test stimuli and test responses for a particul ar core have to be transported over these test buses. The core might requir e more widths for input and output than test buses, and hence, for some par t of the test, the TANIs are idle;, this is a wasteful usage of the TANIs. In this paper, an optimization method of test accesses with a combined BIST * and external test (CBET) scheme is proposed for eliminating the wasteful usage of test buses. This method can minimize the test time and eliminate t he wasteful usage of external pins by considering the trade-off between tes t time and the number of external pins. Our idea consists of two parts. One is to determine the optimum groups, each of which consists of cores, to si multaneously share mechanisms for the external test. The other is to determ ine the optimum bandwidth of the external input and output for the external test. Our idea is basically formulated for the purpose of eliminating the wasteful external pin usage. We make the external test part to be under the full bandwidth of external pins by considering the trade-off between the t est time and the number of external pins. This is achieved only with the CB ET scheme because it permits test sets for both the BIST and the external t est to be elastic. Taking test bus architecture as an example, a formulatio n for test access optimization and experimental results are shown. Experime ntal results reveal that our optimization can achieve a 51.9% reduction in the test time of conventional test scheduling and our proposals are confirm ed to be effective in reducing the test time of system-on-a-chip.