A graph-theoretic approach to minimizing the number of dangerous processors in fault-tolerant mesh-connected processor arrays

Authors
Citation
I. Takanami, A graph-theoretic approach to minimizing the number of dangerous processors in fault-tolerant mesh-connected processor arrays, IEICE T INF, E84D(11), 2001, pp. 1462-1470
Citations number
17
Categorie Soggetti
Information Tecnology & Communication Systems
Journal title
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS
ISSN journal
09168532 → ACNP
Volume
E84D
Issue
11
Year of publication
2001
Pages
1462 - 1470
Database
ISI
SICI code
0916-8532(200111)E84D:11<1462:AGATMT>2.0.ZU;2-5
Abstract
First, we give a graph-theoretic formalization for the spare assignment pro blems for two cases of reconfiguring N x N mesh-connected processor arrays with spares on a diagonal line in the array or two orthogonal lines at the edges of the array. Second, we discuss the problems for minimizing the numb ers of "dangerous processors" for the cases. Here, a dangerous processor is a nonfaulty one for which there remains no spare processor to be assigned if it becomes faulty, without modifying the spare assignments to other faul ty processors. The problem for the latter case, originally presented by Mel hem [1], [2], has already been discussed and solved by the O(N-2) algorithm in [3], but it's procedure is very complicated. Using the above graph-theo retic formalization, we give efficient plain algorithms for minimizing the numbers of dangerous processors by which the problems for both the cases ca n be solved in O(N) time.