VLSI yield optimization based on the redundancy at the sub-processing-element level

Citation
Tx. Zhao et al., VLSI yield optimization based on the redundancy at the sub-processing-element level, IEICE T INF, E84D(11), 2001, pp. 1471-1475
Citations number
7
Categorie Soggetti
Information Tecnology & Communication Systems
Journal title
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS
ISSN journal
09168532 → ACNP
Volume
E84D
Issue
11
Year of publication
2001
Pages
1471 - 1475
Database
ISI
SICI code
0916-8532(200111)E84D:11<1471:VYOBOT>2.0.ZU;2-3
Abstract
An optimal allocation model for the sub-processing-element (sub-PE) level r edundancy is developed, which is solved by the genetic algorithms. In the a llocation model, the average defect density D and the parameter delta are a lso considered in order to accurately analyze the element yield, where delt a is defined as the ratio of the support circuit area to the total area of a PE. When the PE's area is imposed on the constraint, the optimal solution s of the model with different D and delta are calculated. The simulation re sults indicate that, for any fixed average defect density D, both the numbe r of the optimal redundant sub-circuit added into a PE and the PE's yield d ecrease as delta increases. Moreover, for any fixed parameter delta, the nu mber of the optimal redundant. sub-circuit increases, while the optimal yie ld of the PE decreases, as D increases.