Statistical skew modeling and clock period optimization of wafer scale H-tree clock distribution network

Available statistical skew models are too conservative in estimating the ex pected clock skew of a well-balanced H-tree. New closed form expressions ar e presented for accurately estimating the expected values and the variances of both the clock skew and the largest clock delay of a well-balanced H-tr ee. Based on the new model, clock period optimizations of wafer scale H-tre e clock network are investigated under both conventional clocking mode and pipelined clocking mode. It is found that when the conventional clocking mo de is used, clock period optimization of wafer scale H-tree is reduced to t he minimization of expected largest clock delay under both area restriction and power restriction. On the other hand, when the pipelined clocking mode is considered, the optimization is reduced to the minimization of expected clock skew under power restriction. The results obtained in this paper are very useful in the optimization design of wafer scale H-tree clock distrib ution networks.