New BIST schemes for structural testing of pipelined analog to digital converters

Two alternative BIST schemes are proposed for structural testing of pipelin ed Analog-to-Digital Converters (ADC). They are oriented to fault detection in the converter stages rather than to measure the whole ADC electrical pe rformance parameters. The operational principle of both strategies relies o n testing every ADC stage reconfigured as an A/D-D/A block and applying as input a simple DC stimuli set which is easily obtained, without strong prec ision requirements, by a resistive network. The main differences between bo th strategies relate to the way the output response is evaluated. In the BI ST#1 scheme, analog and digital outputs are compared with reference levels generated with a reference D/A converter and a counter. In the BIST#2 strat egy, only digital outputs are available and they are compared with fault-fr ee values previously stored in an on-chip register. The new techniques are intended to be used in pipelined converters of an arbitrary number of conve rsion stages and with a digital self-correction mechanism.