S. Seshadri et Ja. Abraham, Frequency response verification of analog circuits using global optimization techniques, J ELEC TEST, 17(5), 2001, pp. 395-408
Citations number
15
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS
This paper develops a new formal technique to verify the frequency response
of analog circuits using global optimization techniques. Since simulation-
based approaches are unable to cover the design space, there is a need for
formal approaches to verify large circuits. Drawing parallels from the digi
tal domain, the verification problem in the analog domain is modeled as a n
on-linear optimization problem and solved using global optimization techniq
ues by ensuring that the implementation response is bounded within an envel
ope around the specification. We also address the problem of verifying freq
uency response under the influence of parameter variations. Direct as well
as indirect techniques are illustrated using accurate frequency response mo
dels. Experimental results are presented to show the effectiveness of the p
roposed methodology.