Tail bit implications in advanced 2 transistors-flash memory device reliability

Tail bits appearing during program/erase operation or after retention stres ses are major threats to the floating-gate non-volatile memory reliability. Two transistors (2T)-flash architectures circumvent part of the tail bit i nduced problems of IT-NOR and NAND configurations. However, the tail bits s till represent a point of concern in the 2T-NOR memory reliability, because of the disturbs induced by the application of the inhibition voltage and d uring the charge retention. In this paper the impact of tails bits in 2T-fl ash memory is investigated and it is addressed how to face them from the pr ocess point of view. (C) 2001 Elsevier Science B.V. All rights reserved.