In this paper, the compact poly-CMP cell concept is presented as a good can
didate for scaled embedded flash memory in future mainstream CMOS technolog
ies, In this compact cell concept the access gate is placed next to the sta
cked gate transistor. The access gate has a flat top surface due to the use
of chemical mechanical polishing (CMP) and therefore no depth of focus pro
blems with the exposure of the access gate mask occur. The feasibility is p
roven by electrical results on mini arrays in 0.25-mum CMOS technology. Bot
h Fowler-Nordheim tunneling and source side injection programming is possib
le. The program and erase degradation is investigated by endurance cycling.
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