Ultra-shallow junction formation with high process controllability by using optimized RTA process

Implant and RTA (Rapid Thermal Annealing) are investigated for S/D (Source/ Drain) formation process. Optimization of RTA conditions is the key for ult ra-shallow junction formation. This paper describes the ultra-shallow junct ion formation by using RTA. We investigate the effects of thermal budget su ch as ramp-up rate and ramp-down rate, oxygen content and cap-films during the RTA process for achieving shallow junction and low sheet-resistance. In addition, we investigate the effects of these parameters on process contro llability and on the combination of CMOS fabrication. By using optimized RT A technology, shallow junctions with low sheet-resistance and good process controllability for early 100nm technology node can be achieved.