A functional memory implementation of the M-Max NLMS adaptive algorithm

The partial-update M-Max NLMS adaptive algorithm has been shown to have per formance closer to that of the full-update NLMS algorithm than any other al gorithm with reduced number of multiply\adds for a given number of updates. The algorithm entails sorting out the input absolute data vector at each s ample time. In this paper. a hardware running sorter based on a functional memory (FM) architecture is presented. Running sorting is an operation that is crucial to other applications like nonlinear filtering and Trellis-code search techniques. The proposed approach accelerates operations, thus givi ng the new hardware the capability of completing the running sorting in log N + 7 CPU cycles, A flexible hardware structure for the M-Max NLMS algorit hm is proposed in conjunction with the running sorting design. This allows real-time implementation for very large N. Details of the units in the prop osed hardware are explained. and a functional description of its operation is provided. Such an implementation is economically feasible with current t echnology.