Dynamic pipeline design of an adaptive binary arithmetic coder

Arithmetic coding is an attractive technique for lossless data compression but it tends to be slow. In this paper, a dynamic pipelined very large scal e integration architecture with high performance for on-line adaptive binar y arithmetic coding is presented. To obtain a high throughput pipelined arc hitecture, we first analyze the computation flow of the coding algorithm an d modify the operations whose data and/or control dependencies cause the di fficulties in pipelining. Then, a novel technique called dynamic pipelining is developed to pipeline the coding process with variant (or run-time dete rmined) pipeline latencies (or data initialization intervals) efficiently. As for data path design, a systematic design methodology of high level synt hesis and a less-area but faster fixed-width multiplier are applied, which make the architecture with a little additional hardware. The dynamic pipeli ned architecture has been designed and simulated in Verilog HDL, and its la yout has also been implemented with the 0.8-mum SPDM CMOS process and the I TRI-CCL cell library. Its simulated compression speeds under working freque ncies of 25 and 50 MHz are about 6 and 12.5 Mb/s, respectively. About two t imes the speedup with 30% hardware overhead relative to the original sequen tial one is achieved.