Noise optimization of an inductively degenerated CMOS low noise amplifier

Authors
Andreani, P Sjoland, H
Citation
P. Andreani et H. Sjoland, Noise optimization of an inductively degenerated CMOS low noise amplifier, IEEE CIR-II, 48(9), 2001, pp. 835-841
Citations number
14
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
ISSN journal
10577130 → ACNP
Volume
48
Issue
9
Year of publication
2001
Pages
835 - 841
Database
ISI
SICI code
1057-7130(200109)48:9<835:NOOAID>2.0.ZU;2-E
Abstract
This paper presents a technique for substantially reducing the noise of a C MOS low noise amplifier implemented in the inductive source degeneration to pology. The effects of the gate induced current noise on the noise performa nce are taken into account, and the total output noise is strongly reduced by inserting a capacitance of appropriate value in parallel with the amplif ying MOS transistor of the LNA. As a result, very low noise figures become possible already at very low power consumption levels.