A modified shuffle-free architecture for linear convolution

This paper presents a class of modified parallel very large scale integrati on architectures for linear convolution in shuffle-free forms. The proposed algorithms show that for 1-D convolution, the number of lower-order convol utions can be reduced from three to two allowing a hardware saving without slowing down the processing speed. The proposed partitioning, strategy resu lts in a core of data-independent convolution computations. Such computatio ns can be overlapped in software pipelines, super pipelines, or executed co ncurrently on multiple functional units in a DSP chip.