A low-power array multiplier using separated multiplication technique

This brief proposes a separated multiplication technique that can be used i n digital image signal processing such as finite impulse response (FIR) fil ters to reduce the power dissipation. Since the 2-D image data have high sp atial redundancy, such that the higher bits of input pixels are hardly chan ged, the redundant multiplication of higher bits is avoided by separating m ultiplication into higher and lower parts. The calculated values of the hig her bits are stored in memory cells, caches, such that they can be reused w hen a cache hit occurs. Therefore, the dynamic power is reduced by about 14 % in multipliers by using the proposed separated multiplication technique (SMT) and in a 1-D 4-tap FTR filter by about 10%.