The anticipated explosive growth of pervasive and mobile computing devices
that are typically constrained by energy has brought hardware and software
techniques for energy conservation into the spotlight. While there have bee
n several studies and proposals for energy conservation for CPUs and periph
erals, energy optimization techniques for selective operating mode control
of DRAMs have not been fully explored. It has been shown that, for some sys
tems, as much as 90 percent of overall system energy (excluding I/O) is con
sumed by the DRAM modules, thus, they serve as a good candidate for energy
optimizations. Further, DRAM technology has also matured to provide several
low energy operating modes (power modes), making it an opportunistic momen
t to conduct studies exploring the potential benefits of mode control techn
iques. This paper conducts an in-depth investigation of software and hardwa
re techniques to take advantage of the DRAM mode control capabilities at a
module granularity for energy savings. Using a memory system architecture c
apturing five different energy modes and corresponding resynchronization ti
mes, this paper presents several novel compilation techniques to both clust
er the data across memory banks as well as to detect module idleness and pe
rform energy mode transitions. In addition, hardware-assisted approaches (c
alled self-monitoring) based on predictions of module interaccess times are
proposed. These techniques are extensively evaluated using a set of a doze
n benchmarks, It is shown that we get an average of 61 percent savings in D
RAM energy using compiler-directed mode control. One of the self-monitored
approaches gives as much as 89 percent savings (72 percent on the average),
coming as close as 8.8 percent to the optimal energy savings that one can
expect with DRAM module mode control. The optimization techniques are demon
strated to be invaluable for energy savings as memory technologies continue
to evolve.