PHYSICAL PERFORMANCE LIMITS FOR SHARED BUFFER ATM SWITCHES

Performance studies, linking ATM switch capabilities to physical limit ations imposed by integrated circuit technology, have been scarce, Thi s paper explores trends in circuit capabilities, and makes projections toward the 0.25-mu m technologies that will be available to all switc h designers in the year 2000, The limits imposed by circuit technology are applied to shared buffer ATM switches, We determine requirements and physical limits for buffer capacity, buffer throughput, chip I/O t hroughput, and power dissipation, As a result, we are able to project chip counts, aggregate switch throughputs, and switch dimensions, As w ell, performance capabilities of single-chip shared buffer switches ar e estimated, A single-chip shared buffer switch implemented in 0.25-mu m technology will be capable of an aggregate throughput of 1.3 Tb/s, will accomplish almost arbitrarily low cell loss rates for bursty traf fic, and may be integrated together with translation tables supporting hundreds of connections per port.