The tremendous advantages of adequate 2D/3D device simulations for ESD opti
mization are demonstrated. The pre-silicon ESD-protection concept of a new
CMOS technology was completely based on high-current I-V characteristics si
mulated for different NMOS variations. Silicon verification proved the exce
llent simulation quality of the electrical behavior and. furthermore, gives
an idea of ESD thresholds and their dependencies on layout and technology
parameters. (C) 2001 Elsevier Science Ltd. All rights reserved.