Design alternatives for virtual interface architecture and an implementation on IBM netfinity NT cluster

Citation
M. Banikazemi et al., Design alternatives for virtual interface architecture and an implementation on IBM netfinity NT cluster, J PAR DISTR, 61(11), 2001, pp. 1512-1545
Citations number
24
Categorie Soggetti
Computer Science & Engineering
Journal title
JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING
ISSN journal
07437315 → ACNP
Volume
61
Issue
11
Year of publication
2001
Pages
1512 - 1545
Database
ISI
SICI code
0743-7315(200111)61:11<1512:DAFVIA>2.0.ZU;2-C
Abstract
The Virtual Interface Architecture (VIA) specification has been developed t o standardize user-level network interfaces that provide low-latency. high- bandwidth communications. Few hardware and software implementations of VIA exist. Since the VIA specification is flexible, different choices exist for implementing various components of VIA such as doorbells. address translat ion methods, and completion queues. Although previous studies have evaluate d the overall performance of different VIA implementations. there has not b een a comparative study on the performance of VIA components. In this paper . we evaluate and compare the performance of different implementations of e ssential VIA components. We discuss the pros and coils of each design appro ach and describe the required support for implementing each of them. Then, we discuss an experimental implementation of the Virtual Interface Architec ture for the IBM SP Switch-Connected NT cluster. one of the newest clusteri ng platforms available. We discuss different design issues involved in this implementation. In particular. we explain how the virtual-to-physical addr ess translation is implemented efficiently with a minimum Network Interface Card (NIC) memory requirement. We show how caching the VIA descriptors on the NIC can reduce the communication latency. We also present an efficient scheme for implementing the VIA doorbells without any hardware support. We provide a comprehensive performance evaluation study and discuss the impact of several hardware improvements on the performance of our implementation. The performance of the implemented VIA surpasses that of other existing so ftware implementations of the VIA and is comparable to that of a hardware V IA implementation. The peak measured bandwidth for our system is 101.4 MByt es/s and the one-way latency for short messages is 18.2 mus. (C) 2001 Acade mic Press.