Parametrized and reusable VLSI macro cells for the low-power realization of 2-D discrete-cosine-transform

The problem of an efficient VLSI realization of the 2-D discrete-cosine-tra nsform and its inverse is addressed in this paper. Two circuits implementin g both functions are discussed and characterized from the high-level archit ectural choices down to the gate-level synthesis on different standard-cell target technologies. The circuits are designed as parametric intellectual property (IP) cells according to a design reuse policy that allows the user to select the most convenient solution for the considered application. Syn thesis results show that the circuits are suitable for real time processing of various image formats adopted in H.263/MPEG compression standards. Powe r consumption reduction methods (clock gating, switching activity reduction ) are used according to the statistics of the input signals to reduce the d issipated power. The effects of supply voltage scaling and its consequence on circuit performance are examined in detail, as well as the use of differ ent target technologies. Finally, a comparison with dedicated full-custom l ow-power circuits presented in the literature show that these IP cells stan d for flexibility, parametrization and reusability, still maintaining compa rable power consumption and area occupation. (C) 2001 Elsevier Science Ltd. All rights reserved.