A novel approach to high-level switching activity modeling with applications to low-power DSP system synthesis

We address high-level synthesis of low-power digital signal processing (DSP ) systems by using efficient switching activity models. We present a techno logy-independent hierarchical scheme that can be easily integrated into cur rent communications/DSP CAD tools for comparing the relative power/performa nce of two competing DSP designs without specific knowledge of transistor-l evel details. The basic building blocks considered for such systems are a f ull adder, a half adder, and a one-bit delay. Estimates of the switching ac tivity at the output of these primitives are used to model the activity in more complex building blocks of DSP systems. The presented hierarchical met hod is very fast and simple. The accuracy of estimates obtained using the p roposed approach is shown to be within 4% of the results obtained using ext ensive bit-level simulations. Our approach shows that the choice of multipl ier/multiplicand is important when using array multipliers in a datapath. I f the input signal with smaller mean square value is chosen as the multipli cand, almost 20% savings in switching activity can be achieved. This observ ation is verified by an analog simulation using a 16 x 16 bit array multipl ier implemented in a 0.6-mu process with 3.3 V supply voltage.