Analytical models and performance analyses of instruction fetch on superscalar processors

Cache memories are small fast memories used to temporarily hold the content s of main memory that are likely to be referenced by processors so as to re duce instruction and data access time. Tn study of cache performance, most of previous works have employed simulation-based methods. However, that kin d of researches cannot precisely explain the obtained results. Moreover, wh en a new processor is designed, huge simulations must be performed again wi th several different parameters. This research classifies cache structures for superscalar processors into four types, and then represents analytical model of instruction fetch process for each cache type considering various kinds of architectural parameters such as the frequency of branch instructi ons in program, cache miss fate, cache miss penalty, branch misprediction f requency, and branch misprediction penalty, and etc. To prove the correctne ss of the proposed models, we performed extensive simulations and compared the results with the analytical models. Simulation results showed that the proposed model can estimate the expected instruction fetch rate accurately within 10% error in most cases. This paper shows that the increase of cache misses reduces the instruction fetch rate more severely than that of branc h misprediction does. The model is also able to provide exact relationship between cache miss and branch misprediction for the instruction fetch analy sis. The proposed model can explain the causes of performance degradation t hat cannot be uncovered by the simulation method only.