A high-speed multiplier-free realization of IIR filter using ROM's and elevated signal rate

In this paper, we propose a high-speed multiplier-free realization using RO M's to store the results of coefficient scalings in combination with higher signal rate and pipelined operations, without the need of hardware multipl iers. By varying some parameters, the proposed structure provides various c ombinations of hardware and clock speed (or throughput). Examples are given comparing the proposed realization with the distributed arithmetic (DA) re alization and direct-form realization with power-of-two coefficients. Resul ts show that with proper choices of the parameters the proposed structure a chieves a faster processing speed with less hardware, as compared to the DA realization, while it is much faster than the direct-form with slightly mo re hardware.