An accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-adders

Carry-save adder (CSA) is one of the most widely used implementation units for arithmetic circuits. However, the existing approaches to the CSA transf ormation have an inherent limitation in the scope of CSA application, i.e., transforming each of operation trees separately without any interaction am ong them, which results in a locally optimized CSA circuit. To overcome the limitation, we introduce a new concept called tree-boundary optimization t echniques, based on which we propose a practically efficient algorithm for exploring timing and area trade-offs in optimizing arithmetic circuits usin g CSAs. The proposed algorithm is applicable to any arithmetic circuits wit h multiple operation trees, which appear in most filter designs. From exper imentations on a number of digital filter designs, we confirm that the prop osed algorithm reduces the circuit timing by 4%-40% without any area increa se compared to those produced by the conventional CSA transformations.