Programmable multiplierless digital filter array for embedded SoC applications

The authors present a novel, programmable logic array for implementing high performance filter functions within embedded system-on-chip platforms. The novelty of the architecture is demonstrated through its specially tailored configurable logic units, and hierarchical routing scheme. The architectur e and routing hierarchy are described using a filter example and results ar e provided demonstrating scalability, speed, and array utilisation using a typical SoC bus specification.