Demonstration of sub-5 ps CML ring oscillator gate delay with reduced parasitic AlInAs/InGaAs HBT

We have demonstrated a gate delay of 4.9 ps and a power dissipation of 8 mW per CML inverter in an AlInAs/InGaAs HBT technology with 150 mV logic swin g. The demonstration circuit was a 15-stage ring oscillator based on CML in verters with a fan-out of 1 and a nominal 3.1 V supply. The same circuit wa s measured to have a gate delay of 4.7 ps and a power dissipation of 13 mW per inverter using a 3.6 V supply, and a gate delay of 6.2 ps and a power d issipation of 2.4 mW per inverter with a 2.2 V supply. These are the fastes t results for a bipolar transistor based logic family in any semiconductor and comparable to the fastest results for any logic family in any semicondu ctor, Because two gate delays are required for the simplest useful sequenti al logic circuits such as clocked flip-flops, this is a significant milesto ne in that it is the first, though somewhat idealized, demonstration that l ogic at 100 GHz is realizable in InP-based HBT.