Double pocket architecture using indium and boron for sub-100 nm MOSFETs

Citation
S. Odanaka et al., Double pocket architecture using indium and boron for sub-100 nm MOSFETs, IEEE ELEC D, 22(7), 2001, pp. 330-332
Citations number
11
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE ELECTRON DEVICE LETTERS
ISSN journal
07413106 → ACNP
Volume
22
Issue
7
Year of publication
2001
Pages
330 - 332
Database
ISI
SICI code
0741-3106(200107)22:7<330:DPAUIA>2.0.ZU;2-S
Abstract
A double pocket architecture for sub-100 nm MOSFET's is proposed on the bas is of indium pocket profiling at higher hose than the amorphization thresho ld. At high dose, the low-energy indium pockets realize the improvement of short channel effects and shallow extension formation of highly doped drain , maintaining the low junction leakage level. Double pocket architecture us ing indium and boron is demonstrated in a 70 nm gate length MOSFET with hig h drive currents and good control of the short channel effects.